The design of a fully synchronous system on chip is becoming a challenging task, particularly for advanced nodes and 3D designs. Indeed, local and global variability means that the timing closure is becoming an overwhelming task.
The Globally Asynchronous Locally Synchronous (GALS) design style provides a useful alternative to a fully synchronous approach, as it provides improved robustness against local and inter-die variability. For example, asynchronous communications may be implemented using Quasi Delay Insensitive (QDI) protocols, which have the advantage of being almost free of timing constraints. In view of its similarities to standard binary signals, the use of four-phase QDI encoding is often a preferred choice for on chip communications. A four-phase asynchronous protocol involves implementing, for each data symbol to be transmitted, a handshake protocol involving four transmission phases.
A difficulty is that the use of four-phase asynchronous protocols for communications off chip and over 3D interfaces tends to introduce unacceptable interface delays, and leads to high dynamic power consumption.
Two-phase transmissions protocols provide an interesting alternative to four-phase protocols for off chip communications. However, existing two-phase transmission protocols tend to be complex to implement.
There is thus a need in the art for an asynchronous protocol allowing data communications with relatively low interface delays, low dynamic power consumption, and/or permitting relatively high data throughput. There is also a need for relatively simple and compact circuits for implementing such an asynchronous protocol.